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slas312a ? july 2001 ? revised march 2003 1 post office box 655303 ? dallas, texas 75265 low supply voltage range 1.8 v ? 3.6 v ultralow-power consumption: ? active mode: 200 a at 1 mhz, 2.2 v ? standby mode: 0.7 a ? off mode (ram retention): 0.1 a five power saving modes wake-up from standby mode in 6 s 16-bit risc architecture, 125 ns instruction cycle time basic clock module configurations: ? various internal resistors ? single external resistor ? 32 khz crystal ? high frequency crystal ? resonator ? external clock source 16-bit timer_a with three capture/compare registers on-chip comparator for analog signal compare function or slope a/d conversion serial communication interface (usart) software-selects asynchronous uart or synchronous spi serial onboard programming, no external programming voltage needed programmable code protection by security fuse family members include: MSP430F122: 4kb + 256b flash memory 256b ram msp430f123: 8kb + 256b flash memory 256b ram available in a 28-pin plastic small-outline wide body (sowb) package and 28-pin plastic thin shrink small-outline package (tssop) for complete module descriptions, see the msp430x1xx family user?s guide , literature number slau049 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 test v cc p2.5/r osc v ss xout xin rst /nmi p2.0/aclk p2.1/inclk p2.2/caout/tao p3.0/ste0 p3.1/simo0 p3.2/somi0 p3.3/uclk0 p1.7/ta2/tdo/tdi p1.6/ta1/tdi p1.5/ta0/tms p1.4/smclk/tck p1.3/ta2 p1.2/ta1 p1.1/ta0 p1.0/taclk p2.4/ca1/ta2 p2.3/ca0/ta1 p3.7 p3.6 p3.5/urxd0 p3.4/utxd0 dw or pw package (top view) description the texas instruments msp430 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. the architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. the device features a powerful 16-bit risc cpu, 16-bit registers, and constant generators that attribute to maximum code efficiency. the digitally controlled oscillator (dco) allows wake-up from low-power modes to active mode in less than 6 s. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. copyright ? 2001, ? 2003 texas instruments incorporated
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slas312a ? july 2001 ? revised march 2003 2 post office box 655303 ? dallas, texas 75265 description (continued) the msp430f12x series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer and twenty-two i/o pins.the msp430f12x series also has a built-in communication capability using asynchronous (uart) and synchronous (spi) protocols in addition to a versatile analog comparator. typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data and display them or transmit them to a host system. stand alone rf sensor front end is another area of application. the i/o port inputs provide single slope a/d conversion capability on resistive sensors. available options packaged devices t a plastic 28-pin sowb (dw) plastic 28-pin tssop (pw) MSP430F122idw MSP430F122ipw ? 40 c to 85 c MSP430F122idw msp430f123idw MSP430F122ipw msp430f123ipw functional block diagram aclk smclk power-on- reset i/o port p1 cpu incl. 16 reg. test jtag bus conv mab, mdb, mab, 4 bit mdb, 8 bit mcb xin xout v cc v ss rst/nmi p1.0 ? 7 dcor aclk p2.0 / aclk rosc test outx mclk aclk smclk outx ccix ccix taclk inclk inclk out0 cci0 jtag ccixa taclk smclk i/o port p2 6 i/o ? s all with 8 interrupt capabililty comparator_a input multiplexer rc filtered o/p internal vref analog switch p2.1 / inclk p2.2 / caout/ta0 p2.5 / rosc p2.4 / ca1/ta2 p2.3 / ca0/ta1 cci1 + flash info 4kb/8kb flash 8 i/o ? s, all with interrupt capabililty p1.0 ? 7 8 p3.0-7 i/o port p3 256b ram watchdog timer 15/16 bit or cci1 usart uart mode spi mode timer_a 3 cc ccr0/1/2 x = 0, 1, 2 register 16 bit 16 bit oscillator system clock

slas312a ? july 2001 ? revised march 2003 3 post office box 655303 ? dallas, texas 75265 terminal functions terminal name no. i/o description p1.0/taclk 21 i/o general-purpose digital i/o pin/timer_a, clock signal taclk input p1.1/ta0 22 i/o general-purpose digital i/o pin/timer_a, capture: cci0a input, compare: out0 output p1.2/ta1 23 i/o general-purpose digital i/o pin/timer_a, capture: cci1a input, compare: out1 output p1.3/ta2 24 i/o general-purpose digital i/o pin/timer_a, capture: cci2a input, compare: out2 output p1.4/smclk/tck 25 i/o general-purpose digital i/o pin/smclk signal output/test clock, input terminal for device programming and test p1.5/ta0/tms 26 i/o general-purpose digital i/o pin/timer_a, compare: out0 output/test mode select, input terminal for device programming and test p1.6/ta1/tdi 27 i/o general-purpose digital i/o pin/timer_a, compare: out1 output/test data input terminal p1.7/ta2/tdo/tdi ? 28 i/o general-purpose digital i/o pin/timer_a, compare: out2 output/test data output terminal or data input during programming p2.0/aclk 8 i/o general-purpose digital i/o pin/aclk output p2.1/inclk 9 i/o general-purpose digital i/o pin/timer_a, clock signal at inclk p2.2/caout/ta0 10 i/o general-purpose digital i/o pin/timer_a, capture: cci0b input/comparator_a, output p2.3/ca0/ta1 19 i/o general-purpose digital i/o pin/timer_a, compare: out1 output/comparator_a, input p2.4/ca1/ta2 20 i/o general-purpose digital i/o pin/timer_a, compare: out2 output/comparator_a, input p2.5/r osc 3 i/o general-purpose digital i/o pin/input for external resistor that defines the dco nominal frequency p3.0/ste0 11 i/o general digital i/o, slave transmit enable ? usart0/spi mode p3.1/simo0 12 i/o general digital i/o, slave in/master out of usart0/spi mode p3.2/somi0 13 i/o general digital i/o, slave out/master in of usart0/spi mode p3.3/uclk0 14 i/o general digital i/o, external clock input ? usart0/uart or spi mode, clock output ? usart0/spi mode clock input p3.4/utxd0 15 i/o general digital i/o, transmit data out ? usart0/uart mode p3.5/urxd0 16 i/o general digital i/o, receive data in ? usart0/uart mode p3.6 17 i/o general digital i/o p3.7 18 i/o general digital i/o rst /nmi 7 i reset or nonmaskable interrupt input test 1 i select of test mode for jtag pins on port1 v cc 2 supply voltage v ss 4 ground reference xin 6 i input terminal of crystal oscillator xout 5 i/o output terminal of crystal oscillator ? tdo or tdi is selected via jtag instruction.
general-purpose register program counter stack pointer status register constant generator general-purpose register general-purpose register general-purpose register pc/r0 sp/r1 sr/cg1/r2 cg2/r3 r4 r5 r12 r13 general-purpose register general-purpose register r6 r7 general-purpose register general-purpose register r8 r9 general-purpose register general-purpose register r10 r11 general-purpose register general-purpose register r14 r15

slas312a ? july 2001 ? revised march 2003 4 post office box 655303 ? dallas, texas 75265 short-form description cpu the msp430 cpu has a 16-bit risc architecture that is highly transparent to the application. all operations, other than program-flow instructions, are performed as register operations in conjunc- tion with seven addressing modes for source operand and four addressing modes for destina- tion operand. the cpu is integrated with 16 registers that provide reduced instruction execution time. the register-to-register operation execution time is one cycle of the cpu clock. four of the registers, r0 to r3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. the remain- ing registers are general-purpose registers. peripherals are connected to the cpu using data, address, and control buses, and can be handled with all instructions. instruction set the instruction set consists of 51 instructions with three formats and seven address modes. each instruction can operate on word and byte data. table 1 shows examples of the three types of instruction formats; the address modes are listed in table 2. table 1. instruction word formats dual operands, source-destination e.g. add r4,r5 r4 + r5 ??? > r5 single operands, destination only e.g. call r8 pc ?? >(tos), r8 ?? > pc relative jump, un/conditional e.g. jne jump-on-equal bit = 0 table 2. address mode descriptions address mode s d syntax example operation register mov rs,rd mov r10,r11 r10 ?? > r11 indexed mov x(rn),y(rm) mov 2(r5),6(r6) m(2+r5) ?? > m(6+r6) symbolic (pc relative) mov ede,toni m(ede) ?? > m(toni) absolute mov and mem,and tcdat m(mem) ?? > m(tcdat) indirect mov @rn,y(rm) mov @r10,tab(r6) m(r10) ?? > m(tab+r6) indirect autoincrement mov @rn+,rm mov @r10+,r11 m(r10) ?? > r11 r10 + 2 ?? > r10 immediate mov #x,toni mov #45,toni #45 ?? > m(toni) note: s = source d = destination

slas312a ? july 2001 ? revised march 2003 5 post office box 655303 ? dallas, texas 75265 operating modes the msp430 has one active mode and five software selectable low-power modes of operation. an interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. the following six operating modes can be configured by software: active mode am; ? all clocks are active low-power mode 0 (lpm0); ? cpu is disabled aclk and smclk remain active. mclk is disabled low-power mode 1 (lpm1); ? cpu is disabled aclk and smclk remain active. mclk is disabled dco ? s dc-generator is disabled if dco not used in active mode low-power mode 2 (lpm2); ? cpu is disabled mclk and smclk are disabled dco ? s dc-generator remains enabled aclk remains active low-power mode 3 (lpm3); ? cpu is disabled mclk and smclk are disabled dco ? s dc-generator is disabled aclk remains active low-power mode 4 (lpm4); ? cpu is disabled aclk is disabled mclk and smclk are disabled dco ? s dc-generator is disabled crystal oscillator is stopped

slas312a ? july 2001 ? revised march 2003 6 post office box 655303 ? dallas, texas 75265 interrupt vector addresses the interrupt vectors and the power-up starting address are located in the memory with an address range of 0ffffh-0ffe0h. the vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. interrupt source interrupt flag system interrupt word address priority power-up, external reset, watchdog wdtifg (see note1) keyv (see note 1) reset 0fffeh 15, highest nmi, oscillator fault, flash memory access violation nmiifg (see notes 1 and 4) ofifg (see notes 1 and 4) accvifg (see notes 1 and 4) (non)-maskable, (non)-maskable, (non)-maskable 0fffch 14 0fffah 13 0fff8h 12 comparator_a caifg maskable 0fff6h 11 watchdog timer wdtifg maskable 0fff4h 10 timer_a taccr0 ccifg (see note 2) maskable 0fff2h 9 timer_a taccr1 and taccr2 ccifgs, taifg (see notes 1 and 2) maskable 0fff0h 8 usart0 receive urxifg0 maskable 0ffeeh 7 usart0 transmit utxifg0 maskable 0ffech 6 0ffeah 5 0ffe8h 4 i/o port p2 (eight flags ? see note 3) p2ifg.0 to p2ifg.7 (see notes 1 and 2) maskable 0ffe6h 3 i/o port p1 (eight flags) p1ifg.0 to p1ifg.7 (see notes 1 and 2) maskable 0ffe4h 2 0ffe2h 1 0ffe0h 0, lowest notes: 1. multiple source flags 2. interrupt flags are located in the module 3. there are eight port p2 interrupt flags, but only six port p2 i/o pins (p2.0 ? 5) are implemented on the ? 12x devices. 4. (non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot.

slas312a ? july 2001 ? revised march 2003 7 post office box 655303 ? dallas, texas 75265 special function registers most interrupt and module enable bits are collected into the lowest address space. special function register bits that are not allocated to a functional purpose are not physically present in the device. simple software access is provided with this arrangement. interrupt enable 1 and 2 7654 0 ofie wdtie 32 1 rw-0 rw-0 rw-0 address 0h nmiie accvie rw-0 wdtie: watchdog-timer interrupt enable. inactive if watchdog mode is selected. active if watchdog timer is configured in interval timer mode. ofie: oscillator-fault-interrupt enable nmiie: nonmaskable-interrupt enable accvie: flash access violation interrupt enable 7654 0 32 1 address 01h utxie0 urxie0 rw-0 rw-0 urxie0: usart0, uart, and spi receive-interrupt enable utxie0: usart0, uart, and spi transmit-interrupt enable interrupt flag register 1 and 2 7654 0 ofifg wdtifg 32 1 rw-0 rw-1 rw-0 address 02h nmiifg wdtifg: set on watchdog timer overflow (in watchdog mode) or security key violation. reset on v cc power up or a reset condition at the rst /nmi pin in reset mode. ofifg: flag set on oscillator fault nmiifg: set via rst /nmi pin 7654 0 32 1 address 03h utxifg0 urxifg0 rw-0 rw-0 urxifg0: usart0, uart, and spi receive flag utxifg0: usart0, uart, and spi transmit flag

slas312a ? july 2001 ? revised march 2003 8 post office box 655303 ? dallas, texas 75265 module enable registers 1 and 2 7654 0 32 1 address 04h 7654 0 32 1 address 05h utxe0 urxe0 uspie0 rw-0 rw-0 urxe0: usart0, uart receive enable utxe0: usart0, uart transmit enable uspie0: usart0, spi (synchronous peripheral interface) transmit and receive enable legend rw: rw-0: bit can be read and written. bit can be read and written. it is reset by puc sfr bit is not present in device. memory organization int. vector 8 kb flash segment0 ? 15 256b ram 16b per. 8b per. sfr ffffh ffe0h ffdfh 02ffh 0200h 01ffh 0100h 00ffh 0010h 000fh 0000h msp430f123 e000h main memory 10ffh 2 128b flash segmenta,b information memory 1000h 1 kb boot rom 0c00h int. vector 4 kb flash segment0 ? 7 256b ram 16b per. 8b per. sfr ffdfh f000h 02ffh 0200h 0100h 00ffh 0010h 000fh 0000h MSP430F122 1 kb boot rom 2 128b flash segmenta,b 10ffh 1000h 01ffh 0c00h 0fffh ffffh ffe0h 0fffh

slas312a ? july 2001 ? revised march 2003 9 post office box 655303 ? dallas, texas 75265 bootstrap loader (bsl) the msp430 bootstrap loader (bsl) enables users to program the flash memory or ram using a uart serial interface. access to the msp430 memory via the bsl is protected by user-defined password. for complete description of the features of the bsl and its implementation, see the application report features of the msp430 bootstrap loader , literature number slaa089. flash memory the flash memory can be programmed via the jtag port, the bootstrap loader, or in-system by the cpu. the cpu can perform single-byte and single-word writes to the flash memory. features of the flash memory include: flash memory has n segments of main memory and two segments of information memory (a and b) of 128 bytes each. each segment in main memory is 512 bytes in size. segments 0 to n may be erased in one step, or each segment may be individually erased. segments a and b can be erased individually, or as a group with segments 0 ? n. segments a and b are also called information memory. new devices may have some bytes programmed in the information memory (needed for test during manufacturing). the user should perform an erase of the information memory prior to the first use.

slas312a ? july 2001 ? revised march 2003 10 post office box 655303 ? dallas, texas 75265 peripherals peripherals are connected to the cpu through data, address, and control busses and can be handled using all instructions. oscillator and system clock the clock system in the msp430x12x devices is supported by the basic clock module that includes support for a 32768-hz watch crystal oscillator, an internal digitally-controlled oscillator (dco) and a high frequency crystal oscillator. the basic clock module is designed to meet the requirements of both low system cost and low-power consumption. the internal dco provides a fast turn-on clock source and stabilizes in less than 6 s. the basic clock module provides the following clock signals: auxiliary clock (aclk), sourced from a 32768-hz watch crystal or a high frequency crystal. main clock (mclk), the system clock used by the cpu. sub-main clock (smclk), the sub-system clock used by the peripheral modules. digital i/o there are three 8-bit i/o ports implemented ? ports p1, p2, and p3 (only six port p2 i/o signals are available on external pins): all individual i/o bits are independently programmable. any combination of input, output, and interrupt conditions is possible. edge-selectable interrupt input capability for all the eight bits of ports p1 and six bits of port p2. read/write access to port-control registers is supported by all instructions. note: six bits of port p2, p2.0 to p2.5, are available on external pins ? but all control and data bits for port p2 are implemented. port p3 has no interrupt capability. watchdog timer the primary function of the watchdog timer (wdt) module is to perform a controlled system restart after a software problem occurs. if the selected time interval expires, a system reset is generated. if the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. usart0 the msp430x12x devices have one hardware universal synchronous/asynchronous receive transmit (usart0) peripheral module that is used for serial data communication. the usart supports synchronous spi (3 or 4 pin) and asynchronous uart communication protocols, using double-buffered transmit and receive channels. timer_a3 timer_a3 is a 16-bit timer/counter with three capture/compare registers. timer_a3 can support multiple capture/compares, pwm outputs, and interval timing. timer_a3 also has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. comparator_a the primary function of the comparator_a module is to support precision slope analog ? to ? digital conversions, battery ? voltage supervision, and monitoring of external analog signals.

slas312a ? july 2001 ? revised march 2003 11 post office box 655303 ? dallas, texas 75265 peripheral file map peripherals with word access timer_a reserved reserved reserved reserved capture/compare register capture/compare register capture/compare register timer_a register reserved reserved reserved reserved capture/compare control capture/compare control capture/compare control timer_a control timer_a interrupt vector taccr2 taccr1 taccr0 tar tacctl2 tacctl1 tacctl0 tactl taiv 017eh 017ch 017ah 0178h 0176h 0174h 0172h 0170h 016eh 016ch 016ah 0168h 0166h 0164h 0162h 0160h 012eh flash memory flash control 3 flash control 2 flash control 1 fctl3 fctl2 fctl1 012ch 012ah 0128h watchdog watchdog/timer control wdtctl 0120h peripherals with byte access usart0 transmit buffer receive buffer baud rate baud rate modulation control receive control transmit control usart control u0txbuf u0rxbuf u0br1 u0br0 u0mctl u0rctl u0tctl u0ctl 077h 076h 075h 074h 073h 072h 071h 070h comparator_a comparator_a port disable comparator_a control2 comparator_a control1 capd cactl2 cactl1 05bh 05ah 059h basic clock basic clock sys. control2 basic clock sys. control1 dco clock freq. control bcsctl2 bcsctl1 dcoctl 058h 057h 056h port p3 port p3 selection port p3 direction port p3 output port p3 input p3sel p3dir p3out p3in 01bh 01ah 019h 018h port p2 port p2 selection port p2 interrupt enable port p2 interrupt edge select port p2 interrupt flag port p2 direction port p2 output port p2 input p2sel p2ie p2ies p2ifg p2dir p2out p2in 02eh 02dh 02ch 02bh 02ah 029h 028h

slas312a ? july 2001 ? revised march 2003 12 post office box 655303 ? dallas, texas 75265 peripheral file map (continued) peripherals with byte access (continued) port p1 port p1 selection port p1 interrupt enable port p1 interrupt edge select port p1 interrupt flag port p1 direction port p1 output port p1 input p1sel p1ie p1ies p1ifg p1dir p1out p1in 026h 025h 024h 023h 022h 021h 020h special function module enable2 module enable1 sfr interrupt flag2 sfr interrupt flag1 sfr interrupt enable2 sfr interrupt enable1 me2 me1 ifg2 ifg1 ie2 ie1 005h 004h 003h 002h 001h 000h absolute maximum ratings ? voltage applied at v cc to v ss ? 0.3 v to 4.1 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage applied to any pin (referenced to v ss ) ? 0.3 v to v cc +0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . diode current at any device terminal 2 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature, t stg (unprogrammed device) ? 55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature, t stg (programmed device) ? 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note: all voltages referenced to v ss .

slas312a ? july 2001 ? revised march 2003 13 post office box 655303 ? dallas, texas 75265 recommended operating conditions min nom max units supply voltage during program execution, v cc (see note 1) msp430f12x 1.8 3.6 v supply voltage during program/erase flash memory, v cc msp430f12x 2.7 3.6 v supply voltage, v ss 0 v operating free-air temperature range, t a msp430f12x ? 40 85 c lf mode selected, xts=0 watch crystal 32 768 hz lfxt1 crystal frequency, f (lfxt1) ceramic resonator 450 8000 (see note 2) xt1 selected mode, xts=1 crystal 1000 8000 khz v cc = 1.8 v, msp430f12x dc 4.15 processor frequency f (system) (mclk signal) v cc = 3.6 v, msp430f12x dc 8 mhz flash timing generator frequency, f (ftg) msp430f12x 257 476 khz cumulative program time, block write, t (cpt) (see note 3) v cc = 2.7 v/3.6 v msp430f12x 3 ms low-level input voltage (test, rst /nmi), v il (excluding xin, xout) v cc = 2.2 v/3 v v ss v ss +0.6 v high-level input voltage (test, rst /nmi), v ih (excluding xin, xout) v cc = 2.2 v/3 v 0.8v cc v cc v v il(xin, xout) v ss 0.2 v cc input levels at xin, xout v ih(xin, xout) v cc = 2.2 v/3 v 0.8 v cc v cc v notes: 1. the lfxt1 oscillator in lf-mode requires a resistor of 5.1 m ? from xout to v ss when v cc <2.5 v. the lfxt1 oscillator in xt1-mode accepts a ceramic resonator or a crystal frequency of 4 mhz at v cc 2.2 v. the lfxt1 oscillator in xt1-mode accepts a ceramic resonator or a crystal frequency of 8 mhz at v cc 2.8 v. 2. the lfxt1 oscillator in lf-mode requires a watch crystal. the lfxt1 oscillator in xt1-mode accepts a ceramic resonator or a crystal. 3. the cumulative program time must not be exceeded during a block-write operation. 4.15 mhz at 1.8 v msp430f12x devices note: minimum processor frequency is defined by system clock. flash program or erase operations require a minimum v cc of 2.7 v. 9 3 2 1 0 01 2 3 4 4 v cc ? supply voltage ? v 8 mhz at 3.6 v 5 6 7 8 ? maximum processor frequency ? mhz f (system) figure 1. frequency vs supply voltage

slas312a ? july 2001 ? revised march 2003 14 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) supply current (into v cc ) excluding external current parameter test conditions min typ max unit t a = ? 40 c +85 c, f = f = 1 mhz, v cc = 2.2 v 200 250 a i (am) active mode t a = ? 40 c +85 c, v cc = 2.2 v 3 5 a t a = ? 40 c +85 c, v cc = 2.2 v 32 45 a t a = ? 40 c +85 c, v cc = 2.2 v 11 14 a t a = ? 40 c 0.8 1.2 t a = 25 c v cc = 2.2 v 0.7 1 a t a = 85 c cc 1.6 2.3 ? 40 c 1.8 2.2 t a = 25 c v cc = 3 v 1.6 1.9 a t a = 85 c cc 2.3 3.4 ? 40 c 0.1 0.5 i (lpm4) low-power mode, (lpm4) t a = 25 c v cc = 2.2 v/3 v 0.1 0.5 a (lpm4) t a = 85 c cc 0.8 1.9 current consumption of active mode versus system frequency i am = i am[1 mhz] f system [mhz] current consumption of active mode versus supply voltage i am = i am[3 v] + 120 a/v (v cc ? 3 v) schmitt-trigger inputs port p1 to port p3; p1.0 to p1.7, p2.0 to p2.5, p3.0 to p3.7 parameter test conditions min typ max unit v cc = 2.2 v 1.1 1.5 v it+ positive-going input threshold voltage v cc = 3 v 1.5 1.9 v v cc = 2.2 v 0.4 0.9 v it ? negative-going input threshold voltage v cc = 3 v 0.9 1.3 v v cc = 2.2 v 0.3 1.1 v hys input voltage hysteresis, (v it+ ? v it ? ) v cc = 3 v 0.5 1 v

slas312a ? july 2001 ? revised march 2003 15 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs port 1 to p3; p1.0 to p1.7, p2.0 to p2.5, p3.0 to p3.7 parameter test conditions min typ max unit i (ohmax) = ? 1.5 ma see note 1 v cc ? 0.25 v cc i (ohmax) = ? 6 ma v cc = 2.2 v see note 2 v cc ? 0.6 v cc v oh high-level output voltage i (ohmax) = ? 1.5 ma see note 1 v cc ? 0.25 v cc v i (ohmax) = ? 6 ma v cc = 3 v see note 2 v cc ? 0.6 v cc i (olmax) = 1.5 ma see note 1 v ss v ss +0.25 i (olmax) = 6 ma v cc = 2.2 v see note 2 v ss v ss +0.6 v ol low-level output voltage i (olmax) = 1.5 ma see note 1 v ss v ss +0.25 v i (olmax) = 6 ma v cc = 3 v see note 2 v ss v ss +0.6 notes: 1. the maximum total current, i ohmax and i olmax , for all outputs combined, should not exceed 12 ma to hold the maximum voltage drop specified. 2. the maximum total current, i ohmax and i olmax , for all outputs combined, should not exceed 48 ma to hold the maximum voltage drop specified. outputs ? ports p1, p2, and p3 figure 2 v ol ? low-level output voltage ? v 0 4 8 12 16 20 24 28 32 0.0 0.5 1.0 1.5 2.0 2.5 v cc = 2.2 v p1.0 t a = 25 c t a = 85 c ol i ? typical low-level output current ? ma typical low-level output current vs low-level output voltage figure 3 v ol ? low-level output voltage ? v 0 10 20 30 40 50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc = 3 v p1.0 t a = 25 c t a = 85 c typical low-level output current vs low-level output voltage ol i ? typical low-level output current ? ma note: only one output is loaded at a time.

slas312a ? july 2001 ? revised march 2003 16 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs ? ports p1, p2, and p3 (continued) figure 4 v oh ? high-level output voltage ? v ? 28 ? 24 ? 20 ? 16 ? 12 ? 8 ? 4 0 0.0 0.5 1.0 1.5 2.0 2.5 v cc = 2.2 v p1.0 t a = 25 c t a = 85 c oh i ? typical high-level output current ? ma typical high-level output current vs high-level output voltage figure 5 v oh ? high-level output voltage ? v ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc = 3 v p1.0 t a = 25 c t a = 85 c typical high-level output current vs high-level output voltage oh i ? typical high-level output current ? ma note: only one output is loaded at a time. leakage current parameter test conditions v cc min typ max unit port p1: p1.x, 0 7 (see notes 1 and 2) 2.2 v/3 v 50 i lkg(px.x) high-impedance leakage current port p2: p2.x, 0 5 (see notes 1 and 2) 2.2 v/3 v 50 na notes: 1. the leakage current is measured with v ss or v cc applied to the corresponding pin(s), unless otherwise noted. 2. the leakage of the digital port pins is measured individually. the port pin must be selected for input and there must be no o ptional pullup or pulldown resistor.

slas312a ? july 2001 ? revised march 2003 17 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) inputs px.x, tax parameter test conditions v cc min typ max unit 2.2 v/3 v 1.5 cycle t (int) external interrupt timing port p1, p2: p1.x to p2.x, external trigger signal 2.2 v 62 (int) for the interrupt flag, (see note 1) 3 v 50 ns 2.2 v/3 v 1.5 cycle t (cap) timer_a, capture timing ta0, ta1, ta2 (see note 2) 2.2 v 62 (cap) 3 v 50 ns timer_a clock frequency 2.2 v 8 f (taext) timer_a clock frequency externally applied to pin taclk, inclk t (h) = t (l) 3 v 10 mhz 2.2 v 8 f (taint) timer_a clock frequency smclk or aclk signal selected 3 v 10 mhz notes: 1. the external signal sets the interrupt flag every time the minimum t (int) cycle and time parameters are met. it may be set even with trigger signals shorter than t (int) . both the cycle and timing specifications must be met to ensure the flag is set. t (int) is measured in mclk cycles. 2. the external capture signal triggers the capture event every time the mimimum t (cap) cycle and time parameters are met. a capture may be triggered with capture signals even shorter than t (cap) . both the cycle and timing specifications must be met to ensure a correct capture of the 16-bit timer value and to ensure the flag is set. usart (see note 1) parameter test conditions min typ max unit v cc = 2.2 v 200 430 800 t ( ) usart: deglitch time v cc = 3 v 150 280 500 ns note 1: the signal applied to the usart receive signal/terminal (urxd) should meet the timing requirements of t ( ) to ensure that the urxs flip-flop is set. the urxs flip-flop is set with negative pulses meeting the minimum-timing condition of t ( ) . the operating conditions to set the flag must be met independently from this timing constraint. the deglitch circuitry is active only on negative transitio ns on the urxd line. outputs p1.x, p2.x, p3.x, tax parameter test conditions v cc min typ max unit f (p20) p2.0/aclk, c l = 20 pf 2.2 v/3 v f system f (tax) output frequency ta0, ta1, ta2, c l = 20 pf, internal clock source, smclk signal applied (see note 1) 2.2 v/3 v dc f system mhz f smclk = f lfxt1 = f xt1 40% 60% f smclk = f lfxt1 = f lf 35% 65% p1.4/smclk, c l = 20 pf f smclk = f lfxt1/n 2.2 v/3 v 50% ? 15 ns 50% 50%+ 15 ns t (xdc) duty cycle of o/p frequency f smclk = f dcoclk 2.2 v/3 v 50% ? 15 ns 50% 50%+ 15 ns frequency f p20 = f lfxt1 = f xt1 40% 60% p2.0/aclk, f p20 = f lfxt1 = f lf 2.2 v/3 v 30% 70% c l = 20 pf f p20 = f lfxt1/n 50% t (tadc) ta0, ta1, ta2, c l = 20 pf, duty cycle = 50% 2.2 v/3 v 0 50 ns note 1: the limits of the system clock mclk has to be met. mclk and smclk can have different frequencies.

slas312a ? july 2001 ? revised march 2003 18 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) comparator_a (see note 1) parameter test conditions v cc min typ max unit 2.2 v 25 40 a i caon=1, carsel=0, 2.2 v 30 50 a v (ic) common-mode input voltage caon =1 2.2 v/3 v 0 v cc ? 1 v v (ref025) voltage at 0.25 v cc node v cc pca0=1, carsel=1, caref=1, no load at p2.3/ca0/ta1 and p2.4/ca1/ta2 2.2 v/3 v 0.23 0.24 0.25 v (ref050) voltage at 0.5v cc node v cc pca0=1, carsel=1, caref=2, no load at p2.3/ca0/ta1 and p2.4/ca1/ta2 2.2 v/3 v 0.47 0.48 0.5 pca0=1, carsel=1, caref=3, 2.2 v 390 480 540 v (refvt) no load at p2.3/ca0/ta1 and p2.4/ca1/ta2, t a = 85 c 3 v 400 490 550 mv v (offset) offset voltage see note 2 2.2 v/3 v ? 30 30 mv v hys input hysteresis caon=1 2.2 v/3 v 0 0.7 1.4 mv t = 25 c, overdrive 10 mv, without 2.2 v 160 210 300 t a = 25 c, overdrive 10 mv, without filter: caf=0 3 v 80 150 240 ns t (response lh) t = 25 c, overdrive 10 mv, with fil- 2.2 v 1.4 1.9 3.4 s t = 25 c, 2.2 v 130 210 300 t a = 25 c, overdrive 10 mv, without filter: caf=0 3 v 80 150 240 ns t (response hl) t = 25 c, 2.2 v 1.4 1.9 3.4 s notes: 1. the leakage current for the comparator_a terminals is identical to i lkg(px.x) specification. 2. the input offset voltage can be cancelled by using the caex bit to invert the comparator_a inputs on successive measurements. the two successive measurements are then summed together.

slas312a ? july 2001 ? revised march 2003 19 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) t a ? free-air temperature ? c 400 450 500 550 600 650 ? 45 ? 25 ? 51535557595 v cc = 3 v figure 6. v (refvt) vs temperature, v cc = 3 v v (refvt) ? reference volts ? mv typical figure 7. v (refvt) vs temperature, v cc = 2.2 v t a ? free-air temperature ? c 400 450 500 550 600 650 ? 45 ? 25 ? 51535557595 v cc = 2.2 v v (refvt) ? reference volts ? mv typical _ + caon 0 1 v+ 0 1 caf low pass filter 2.0 s to internal modules set caifg flag caout v ? v cc 1 0 v 0 figure 8. block diagram of comparator_a module overdrive v caout t (response) v+ v ? 400 mv figure 9. overdrive definition

slas312a ? july 2001 ? revised march 2003 20 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) puc/por parameter test conditions min typ max unit t (por_delay) 150 250 s t a = ? 40 c 1.4 1.8 v v por por t a = 25 c 1.1 1.5 v por t a = 85 c v cc = 2.2 v/3 v 0.8 1.2 v v (min) 0 0.4 v t (reset) puc/por reset is accepted internally 2 s v cc por v t v por v (min) por no por figure 10. power-on reset (por) vs supply voltage 0 0.2 0.6 1.0 1.2 1.8 2.0 ? 40 ? 20 0 20 40 60 80 temperature [ c] v [v] 1.6 1.4 0.8 0.4 1.2 1.5 1.8 0.8 1.1 1.4 25 c max min por figure 11. v por vs temperature ram parameter min nom max unit v (ramh) cpu halted (see note 1) 1.6 v note 1: this parameter defines the minimum supply voltage v cc when the data in the program memory ram remains unchanged. no program execution should happen during this supply voltage condition.

slas312a ? july 2001 ? revised march 2003 21 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) crystal oscillator,lfxt1 parameter test conditions v cc min typ max unit xts=0; lf mode selected 2.2 v / 3 v 12 c (xin) input capacitance xts=1; xt1 mode selected (see note 1) 2.2 v / 3 v 2 pf xts=0; lf mode selected 2.2 v / 3 v 12 c (xout) output capacitance xts=1; xt1 mode selected (see note 1) 2.2 v / 3 v 2 pf note 1: requires external capacitors at both terminals. values are specified by crystal manufacturers. dco parameter test conditions v cc min typ max unit 2.2 v 0.08 0.12 0.15 f (dco03) r sel = 0, dco = 3, mod = 0, dcor = 0, t a = 25 c 3 v 0.08 0.13 0.16 mhz c 3 v 0.14 0.18 0.22 mhz c 3 v 0.22 0.28 0.34 mhz c 3 v 0.37 0.47 0.56 mhz c 3 v 0.61 0.75 0.9 mhz c 3 v 1 1.3 1.5 mhz c 3 v 1.69 2 2.29 mhz 2.2 v 2.4 2.9 3.4 f (dco73) r sel = 7, dco = 3, mod = 0, dcor = 0, t a = 25 c 3 v 2.7 3.2 3.65 mhz c 3 v 4.4 4.9 5.4 mhz c 2.2 v/3 v f dco40 x1.7 f dco40 x2.1 f dco40 x2.5 mhz s (rsel) s r = f rsel+1 /f rsel 2.2 v/3 v 1.35 1.65 2 s (dco) s dco = f dco+1 /f dco 2.2 v/3 v 1.07 1.12 1.16 ratio 2.2 v ? 0.31 ? 0.36 ? 0.40 ? 0.33 ? 0.38 ? 0.43 %/ c d v drift with v cc variation, r sel = 4, dco = 3, mod = 0 (see note 1) 2.2 v/3 v 0 5 10 %/v notes: 1. these parameters are not production tested.

slas312a ? july 2001 ? revised march 2003 22 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) ?????? ?????? ?????? ?????? 2.2 v 3 v v cc max min max min f (dcox7) f (dcox0) frequency variance 012 34567 dco steps 1 f dcoclk figure 12. dco characteristics principle characteristics of the dco individual devices have a minimum and maximum operation frequency. the specified parameters for f dcox0 to f dcox7 are valid for all devices the dco control bits dco0, dco1 and dco2 have a step size as defined in parameter s dco . the modulation control bits mod0 to mod4 select how often f dco+1 is used within the period of 32 dcoclk cycles. f dco is used for the remaining cycles. the frequency is an average = f dco (2 mod/32 ). all ranges selected by r sel(n) overlap with r sel(n+1) : r sel0 overlaps with r sel1 , ... r sel6 overlaps with r sel7 . wake-up from lower power modes (lpmx) parameter test conditions min typ max unit t (lpm0) v cc = 2.2 v/3 v 100 t (lpm2) v cc = 2.2 v/3 v 100 ns f (mclk) = 1 mhz, v cc = 2.2 v/3 v 6 t (lpm3) f (mclk) = 2 mhz, v cc = 2.2 v/3 v 6 s (lpm3) delay time (see note 1) f (mclk) = 3 mhz, v cc = 2.2 v/3 v 6 s (lpm4) f (mclk) = 3 mhz, v cc = 2.2 v/3 v 6

slas312a ? july 2001 ? revised march 2003 23 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) jtag, program memory and fuse parameter test conditions min typ max unit v cc = 2.2 v dc 5 f (tck) tck frequency, jtag/test (see note 3) v cc = 3 v dc 10 mhz v cc(fb) supply voltage during fuse-blow condition, t (a) = 25 c 2.5 v v (fb) fuse blow voltage (see notes 1 and 2) 6 7 v i (fb) supply current on test during fuse blow (see note 2) 100 ma t (fb) time to blow the fuse (see note 2) 1 ms i (dd-pgm) current during program cycle (see note 4) v cc = 2.7 v/3.6 v 3 5 ma i (dd-erase) current during erase cycle (see note 4) v cc = 2.7 v/3.6 v 3 7 ma write/erase cycles 10 4 10 5 t (retention) data retention t j = 25 c 100 year notes: 1. the power source to blow the fuse is applied to test pin. 2. once the jtag fuse is blown, no further access to the msp430 jtag/test feature is possible. the jtag block is switched to byp ass mode. 3. f (tck) may be restricted to meet the timing requirements of the module selected. 4. f (tck) may be restricted to meet the timing requirements of the module selected. duration of the program/erase cycle is determined by f (ftg) applied to the flash timing controller. it can be calculated as follows: t (word write) = 35 1/f (ftg) t (block write, byte 0) = 30 1/f (ftg) t (block write, bytes 1 ? 63) = 20 1/f (ftg) t (block write end sequence) = 6 1/f (ftg) t (mass erase) = 5297 1/f (ftg) t (segment erase) = 4819 1/f (ftg)

slas312a ? july 2001 ? revised march 2003 24 post office box 655303 ? dallas, texas 75265 application information input/output schematic port p1, p1.0 to p1.3, input/output with schmitt-trigger en d p1.0/taclk p1.1/ta0 p1.2/ta1 p1.3/ta2 0 1 0 1 interrupt edge select en set q p1ie.x p1ifg.x p1irq.x interrupt flag p1ies.x p1sel.x module x in p1in.x p1out.x module x out direction control from module p1dir.x p1sel.x pad logic note: x = bit/identifier, 0 to 3 for port p1 p1sel.0 p1dir.0 p1dir.0 p1out.0 v ss p1in.0 taclk ? p1ie.0 p1ifg.0 p1ies.0 p1sel.1 p1dir.1 p1dir.1 p1out.1 out0 signal ? p1in.1 cci0a ? p1ie.1 p1ifg.1 p1ies.1 p1sel.2 p1dir.2 p1dir.2 p1out.2 out1 signal ? p1in.2 cci1a ? p1ie.2 p1ifg.2 p1ies.2 p1sel.3 p1dir.3 p1dir.3 p1out.3 out2 signal ? p1in.3 cci2a ? p1ie.3 p1ifg.3 p1ies.3 ? signal from or to timer_a

slas312a ? july 2001 ? revised march 2003 25 post office box 655303 ? dallas, texas 75265 application information port p1, p1.4 to p1.7, input/output with schmitt-trigger and in-system access features en d p1.4 ? p1.7 0 1 0 1 interrupt edge select en set q p1ie.x p1ifg.x p1irq.x interrupt flag p1ies.x p1sel.x module x in p1in.x p1out.x module x out direction control from module p1dir.x p1sel.x pad logic bus keeper 60 k ? control by jtag 0 1 tdo controlled by jtag p1.x tdi p1.x tst tms tst tck tst controlled by jtag tst p1.x p1.x note: the test pin should be protected from potential emi and esd voltage spikes. this may require a smaller external pulldown resistor in some applications. x = bit identifier, 4 to 7 for port p1 during programming activity and during blowing the fuse, the pin tdo/tdi is used to apply the test input for jtag circuitry. p1.7/ta2/tdo/tdi p1.6/ta1/tdi p1.5/ta0/tms p1.4/smclk/tck typical test bum and test fuse dv cc p1sel.4 p1dir.4 p1dir.4 p1out.4 smclk p1in.4 unused p1ie.4 p1ifg.4 p1ies.4 p1sel.5 p1dir.5 p1dir.5 p1out.5 out0 signal ? p1in.5 unused p1ie.5 p1ifg.5 p1ies.5 p1sel.6 p1dir.6 p1dir.6 p1out.6 out1 signal ? p1in.6 unused p1ie.6 p1ifg.6 p1ies.6 p1sel.7 p1dir.7 p1dir.7 p1out.7 out2 signal ? p1in.7 unused p1ie.7 p1ifg.7 p1ies.7 ? signal from or to timer_a

slas312a ? july 2001 ? revised march 2003 26 post office box 655303 ? dallas, texas 75265 application information port p2, p2.0 to p2.2, input/output with schmitt-trigger en d p2.0/aclk p2.1/inclk p2.2/caout/ta0 0 1 0 1 interrupt edge select en set q p2ie.x p2ifg.x p2irq.x interrupt flag p2ies.x p2sel.x module x in p2in.x p2out.x module x out direction control from module p2dir.x p2sel.x pad logic note: x = bit identifier, 0 to 2 for port p2 0: input 1: output bus keeper capd.x pnsel.x pndir.x direction control from module pnout.x module x out pnin.x module x in pnie.x pnifg.x pnies.x p2sel.0 p2dir.0 p2dir.0 p2out.0 aclk p2in.0 unused p2ie.0 p2ifg.0 p1ies.0 p2sel.1 p2dir.1 p2dir.1 p2out.1 v ss p2in.1 inclk ? p2ie.1 p2ifg.1 p1ies.1 p2sel.2 p2dir.2 p2dir.2 p2out.2 caout p2in.2 cci0b ? p2ie.2 p2ifg.2 p1ies.2 ? signal from or to timer_a

slas312a ? july 2001 ? revised march 2003 27 post office box 655303 ? dallas, texas 75265 application information port p2, p2.3 to p2.4, input/output with schmitt-trigger en d p2.3/ca0/ta1 0 1 0 1 interrupt edge select en set q p2ie.3 p2ifg.3 p2irq.3 interrupt flag p2ies.3 p2sel.3 module x in p2in.3 p2out.3 module x out direction control from module p2dir.3 p2sel.3 pad logic 0: input 1: output bus keeper capd.3 en d p2.4/ca1/ta2 1 0 1 0 interrupt edge select en set q p2ie.4 p2ifg.4 p2irq.4 interrupt flag p2ies.4 p2sel.4 module x in p2in.4 p2out.4 module x out direction control from module p2dir.4 p2sel.4 pad logic 0: input 1: output bus keeper capd.4 _ + comparator_a reference block caref caref caex p2ca caf cci1b 0 v pnsel.x pndir.x direction control from module pnout.x module x out pnin.x module x in pnie.x pnifg.x pnies.x p2sel.3 p2dir.3 p2dir.3 p2out.3 out1 signal ? p2in.3 unused p2ie.3 p2ifg.3 p1ies.3 p2sel.4 p2dir.4 p2dir.4 p2out.4 out2 signal ? p2in.4 unused p2ie.4 p2ifg.4 p1ies.4 ? signal from timer_a

slas312a ? july 2001 ? revised march 2003 28 post office box 655303 ? dallas, texas 75265 application information port p2, p2.5, input/output with schmitt-trigger and r osc function for the basic clock module en d p2.5/r osc 0 1 0 1 interrupt edge select en set q p2ie.5 p2ifg.5 p2irq.5 interrupt flag p2ies.5 p2sel.5 module x in p2in.5 p2out.5 module x out direction control from module p2dir.5 p2sel.5 pad logic note: dcor: control bit from basic clock module if it is set, p2.5 is disconnected from p2.5 pad bus keeper 0 1 0 1 v cc internal to basic clock module dcor dc generator 0: input 1: output capd.5 pnsel.x pndir.x direction control from module pnout.x module x out pnin.x module x in pnie.x pnifg.x pnies.x p2sel.5 p2dir.5 p2dir.5 p2out.5 v ss p2in.5 unused p2ie.5 p2ifg.5 p2ies.5

slas312a ? july 2001 ? revised march 2003 29 post office box 655303 ? dallas, texas 75265 application information port p2, unbonded bits p2.6 and p2.7 en d 0 1 0 1 interrupt edge select en set q p2ie.x p2ifg.x p2irq.x interrupt flag p2ies.x p2sel.x module x in p2in.x p2out.x module x out direction control from module p2dir.x p2sel.x bus keeper 0 1 0: input 1: output node is reset with puc puc note: x = bit/identifier, 6 to 7 for port p2 without external pins p2sel.x p2dir.x direction- control from module p2out.x module x out p2in.x module x in p2ie.x p2ifg.x p2ies.x p2sel.6 p2dir.6 p2dir.6 p2out.6 v ss p2in.6 unused p2ie.6 p2ifg.6 p2ies.6 p2sel.7 p2dir.7 p2dir.7 p2out.7 v ss p2in.7 unused p2ie.7 p2ifg.7 p2ies.7 note: unbonded bits 6 and 7 of port p2 can be used as interrupt flags. only software can affect the interrupt flags. they work a s software interrupts.

slas312a ? july 2001 ? revised march 2003 30 post office box 655303 ? dallas, texas 75265 application information port p3, p3.0 and p3.4 to p3.7, input/output with schmitt-trigger p3.0/ste0 p3in.x module x in pad logic en d p3out.x p3dir.x p3sel.x module x out direction control from module 0 1 0 1 p3.4/utxd0 p3.5/urxd0 0: input 1: output x: bit identifier, 0 and 4 to 7 for port p3 p3.6 p3.7 pnsel.x pndir.x direction control from module pnout.x module x out pnin.x module x in p3sel.0 p3dir.0 v ss p3out.0 v ss p3in.0 ste0 p3sel.4 p3dir.4 v cc p3out.4 utxd0 ? p3in.4 unused p3sel.5 p3dir.5 v ss p3out.5 v ss p3in.5 urxd0 ? p3sel.6 p3dir.6 v ss p3out.6 v ss p3in.6 unused p3sel.7 p3dir.7 v ss p3out.7 v ss p3in.7 unused ? output from usart0 module ? input to usart0 module port p3, p3.1, input/output with schmitt-trigger p3.1/simo0 p3in.1 pad logic en d p3out1 p3dir.1 p3sel.1 (si)mo0 0 1 0 1 dcm_simo sync mm ste stc from usart0 si(mo)0 to usart0 0: input 1: output

slas312a ? july 2001 ? revised march 2003 31 post office box 655303 ? dallas, texas 75265 application information port p3, p3.2, input/output with schmitt-trigger p3.2/somi0 p3in.2 pad logic en d p3out.2 p3dir.2 p3sel.2 0 1 0 1 dcm_somi sync mm ste stc so(mi)0 from usart0 (so)mi0 to usart0 0: input 1: output port p3, p3.3, input/output with schmitt-trigger p3.3/uclk0 p3in.3 pad logic en d p3out.3 p3dir.3 p3sel.3 uclk.0 0 1 0 1 dcm_uclk sync mm ste stc from usart0 uclk0 to usart0 0: input 1: output note: uart mode: the uart clock can only be an input. if uart mode and uart function are selected, the p3.3/uclk0 is always an input. spi, slave mode: the clock applied to uclk0 is used to shift data in and out. spi, master mode: the clock to shift data in and out is supplied to connected devices on pin p3.3/uclk0 (in slave mode).

slas312a ? july 2001 ? revised march 2003 32 post office box 655303 ? dallas, texas 75265 jtag fuse check mode msp430 devices that have the fuse on the test terminal have a fuse check mode that tests the continuity of the fuse the first time the jtag port is accessed after a power-on reset (por). when activated, a fuse check current, a fuse check current, i tf , of 1 ma at 3 v, 2.5 ma at 5 v can flow from from the test pin to ground if the fuse is not burned. care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. when the test pin is taken back low after a test or programming session, the fuse check mode and sense currents are terminated. activation of the fuse check mode occurs with the first negative edge on the tms pin after power up or if the tms is being held low during power up. the second positive edge on the tms pin deactivates the fuse check mode. after deactivation, the fuse check mode remains inactive until another por occurs. after each por the fuse check mode has the potential to be activated. the fuse check current will only flow when the fuse check mode is active and the tms pin is in a low state (see figure 13). therefore, the additional current flow can be prevented by holding the tms pin high (default condition). time tms goes low after por tms i tf i test figure 13. fuse check mode current, msp430f12x note: the code and ram data protection is ensured if the jtag fuse is blown and the 256-bit bootloader access key is used. also see the bootstrap loader section for more information.

slas312a ? july 2001 ? revised march 2003 33 post office box 655303 ? dallas, texas 75265 mechanical data dw (r-pdso-g**) plastic small-outline package 16 pins shown 4040000 / d 01/00 seating plane 0.400 (10,15) 0.419 (10,65) 0.104 (2,65) max 1 0.012 (0,30) 0.004 (0,10) a 8 16 0.020 (0,51) 0.014 (0,35) 0.291 (7,39) 0.299 (7,59) 9 0.010 (0,25) 0.050 (1,27) 0.016 (0,40) (15,24) (15,49) pins ** 0.010 (0,25) nom a max dim a min gage plane 20 0.500 (12,70) (12,95) 0.510 (10,16) (10,41) 0.400 0.410 16 0.600 24 0.610 (17,78) 28 0.700 (18,03) 0.710 0.004 (0,10) m 0.010 (0,25) 0.050 (1,27) 0 ? 8 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). d. falls within jedec ms-013

slas312a ? july 2001 ? revised march 2003 34 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 ? 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153

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